1. Field
Methods and apparatuses consistent with exemplary embodiments relate to packing source register fields and destination register fields in micro-operations (micro-ops) executed in a microprocessor before a register renaming stage.
2. Description of the Related Art
Modern microprocessors typically break down or translate high-level instructions, e.g. macro instructions, into low-level, hardware-executable micro-ops at decoders provided therein to improve efficiency of data processing. The number and format of decoded micro-ops depend on high-level instruction set architecture and internal microprocessor architecture.
A micro-op typically has two or three source operands and one or two destination operands. The source operands are used to specify registers which contain source data. Destination operands are used to specify registers to which results of an operation of the micro-op are written after the operation has been performed.
The number of source and destination registers for a specific micro-op depends on the type of instruction being executed. For example, an ADD instruction has two source operands and one destination operand. A multiply-accumulate instruction has three source operands and one or more destination operands. A branch instruction has just one source operand to specify an indirect branch address, but has no destination operand. After micro-ops are decoded out, the micro-ops are sent to a renamer where the registers of the micro-ops are renamed before the micro-ops are scheduled and executed. Register renaming is a common technique for elimination of data hazards, such as write-after-read and write-after-write hazards in an out-of-order execution of micro-ops. A renaming process includes checking a rename table for each register, reassigning different or additional physical registers to replace destination registers of the micro-ops, recording data on the dependencies between the micro-ops. The renamed micro-ops are sent to a scheduler and execution unit. The executed micro-ops are then sent to the destination register and/or the memory or cache for storage.
Register renaming is a bottleneck for timing and performance in high-speed microprocessor designs. The limitation is more significant when the number of source and destination registers is increased. In order to optimize overall performance, it is advantageous to maximize the number of micro-ops to be renamed per cycle without increasing the number of rename ports of a renamer.